Current Issue
Volume-1, Issue-2, Jul-Dec-2026
Article-01
Title: Instruction-Level GALS Architecture for Low-Power 8051-Compatible Embedded Systems
Author: Rajakumari Alajangi, N. S. Murthy Sharma, K. Lal Kishore
Pages: 45-57
DOI: https://doi.org/10.55306/CJAMC.2026.010201
Abstract:
Author: Rajakumari Alajangi, N. S. Murthy Sharma, K. Lal Kishore
Pages: 45-57
DOI: https://doi.org/10.55306/CJAMC.2026.010201
Abstract:
This paper discusses the design and implementation of a globally asynchronous, locally synchronous (GALS) 8051 microcontroller with low power consumption and accurate time management for embedded applications. Unlike the traditional 8051 architecture, the proposed design divides the circuit into two local clock domains, thus eliminating the need for a global clock to synchronize the entire circuit and reducing unnecessary clock skew problems and switching requirements. An asynchronous interface technique is implemented in this proposed design to facilitate reliable communication between clock domains, along with incorporating power-aware methodologies, such as selective activation of blocks and clock gating techniques, to make the circuit power efficient. The complete microcontroller circuit, comprising fetch, decode, and execution stages, was designed using Verilog HDL language and synthesized with the help of Genius software from Cadence using GPDK 90 nm technology. A simulation technique was applied to validate the functionality of the design, and its performance was analyzed based on the area, power consumption, and time delays.
Key Words: GALS, 8051-inspired microcontroller, dual-clock architecture, asynchronous handshake, clock domain crossing, power-aware architecture, Internet of Things applications.
Citation: Rajakumari. A. et al, “Instruction-Level GALS Architecture for Low-Power 8051-Compatible Embedded Systems,” Ci-STEM Journal of Advanced Materials and Computing, Vol. 1(2), pp. 45-57, 2026.
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